Displaying 1 - 8 of 8 documents. Show 5 results per page. Committee s : JC This standard will be useful to anyone engaged in handling semiconductor devices and integrated circuits that are subject to permanent damage due to electrostatic potentials. The standard establishes a symbol and label that will gain the attention of those persons who might inflict electrostatic damage to the device.
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Some rush fees may apply. Add to Cart. View Full Details and Buy. Complementary Documents and Links:. This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
These tests are capable of stimulating and precipitating semiconductor device and packaging failure modes on free-standing components not soldered to a printed wired board PWB , or the like base component reliability. The objective is to precipitate failures in an accelerated manner compared to use conditions.
Failure Rate projections usually require larger sample sizes than are called out in qualification testing. This qualification standard is aimed at a generic qualification for a range of use conditions, but may not be applicable at extreme use conditions such as military applications, automotive under-thehood applications, or uncontrolled avionics environments does not cover components assembled onto a PWB, or the like, which may affect the component reliability under assembled state.
This is addressed in JEP and e. This set of tests should not be used indiscriminately. Each qualification project should be examined for: a Any potential new and unique failure mechanisms.
If it is known or suspected that failures either are due to new mechanisms or are uniquely induced by the severity of the test conditions, then the application of the test condition as stated is not recommended. Alternatively, new mechanisms or uniquely problematic stress levels should be addressed by building an understanding of the mechanism and its behavior with respect to accelerated stress conditions Ref. Consideration of PC board assembly-level effects may also be necessary.
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JEDEC JESD 47
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