AT89C52 DATASHEET PDF

The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C52 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.

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The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Pin Configurations. RXD P3. TXD P3. INT0 P3. INT1 P3. T0 P3. T2 P1. T1 P3. WR P3. RD P3. Microcontroller with 8K Bytes Flash.

Not Recommended for New Designs. Use AT89S Block Diagram. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.

The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset. Pin Description. Supply voltage. Port 0. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during Flash program- ming and outputs the code bytes during program verification.

External pullups are required during program verification. Port 1. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs.

As inputs, Port 1 pins that are externally being pulled low will source current I I L because of the internal pullups. In addition, P1. Port 1 also receives the low-order address bytes during Flash programming and verification. Port Pin.

Alternate Functions. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current I I L because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use bit addresses MOVX DPTR. In this application, Port 2 uses strong internal pul- lups when emitting 1s. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current I I L because of the pullups. Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port 3 also receives some control signals for Flash pro- gramming and verification.

RXD serial input port. TXD serial output port. INT0 external interrupt 0. INT1 external interrupt 1. T0 timer 0 external input. T1 timer 1 external input. WR external data memory write strobe. RD external data memory read strobe. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. Note, however, that one ALE pulse is skipped during each access to external data memory. Otherwise, the pin is weakly pulled high.

Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. When the AT89C52 is executing code from external pro-. Table 1. External Access Enable. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to V C C for internal program executions.

This pin also receives the volt programming enable volt- age V P P during Flash programming when volt programming is selected. Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier. Special Function Registers. Note that not all of the addresses are occupied, and unoc- cupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indetermi- nate effect.

User software should not write 1s to these unlisted loca- tions, since they may be used in future products to invoke. Table 2. In that case, the reset or inactive values of the new bits will always be 0. Interrupt Registers The individual interrupt enable bits are in the IE register.

Two priorities can be set for each of the six interrupt sources in the IP register. Bit Addressable. Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. EXF2 must be cleared by software. Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3.

Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Timer or counter select for Timer 2. Data Memory. The upper bytes occupy a parallel address space to the Special Function Registers. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction. Instructions that use direct addressing access SFR space.

MOV 0A0H, data. Instructions that use indirect addressing access the upper bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 whose address is 0A0H. MOV R0, data. Note that stack operations are examples of indirect addressing, so the upper bytes of data RAM are avail- able as stack space.

Timer 0 and 1. Timer 2. The type of operation is. Timer 2 has three operating modes: capture, auto-reload up or down counting , and baud rate generator. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Table 3. Timer 2 Operating Modes. Baud Rate Generator.

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